1. Field of The Invention
The invention relates to methods and apparatus for placement of a probe point at an optimal location for probing of an IC, particularly in a mechanical-probe, electron-beam, focused-ion-beam or laser-beam system.
2. The Prior Art
Charged-particle beam systems are commonly used in verification, characterization, design debug and modification of devices such as integrated circuits. Electron-beam probe (EBP) systems are used to acquire and observe waveforms on internal nodes of a device as the device is exercised by application of a signal pattern to the external pins of the device, and to produce voltage-contrast images of the device.
Focused-ion-beam (FIB) systems are commonly used to perform three major functions: (1) etching/milling of structure, such as for cutting metal lines and drilling holes, (2) depositing material, such as for forming metal connectors and pads, and (3) scanning ion microscope (SIM) observation. These functions may be employed to modify the IC for failure analysis. Cutting and connecting metal lines aids in confirmation of a suspected failure mechanism or failure location, and milling holes in an insulation layer allows a "buried" conductor to be exposed or connected to a pad for improved E-beam or mechanical probing.
FIGS. 1 and 2 show the general structure of a prior-art charged-particle beam system. Commercially-available systems having such a structure include the "IDS 5000.TM." EBP system and "IDS 7000 FIBstation.TM." FIB system, available commercially from Schlumberger Technologies, Inc., of San Jose, Calif. Such systems are described, for example, in U.S. Pat. Nos. 4,706,019 and 4,721,909 to N. Richardson and U.S. Pat. No. 5,140,164 to Talbot et al., the contents of which are incorporated herein by this reference.
A charged-particle beam system 110 has three main functional elements: an electron beam or focused ion beam 112, a circuit exerciser 114, and a data processing system 116 which includes a display terminal 118. Data processing system 116 includes a processor P with associated memory M and a data store D such as a disk drive. Circuit exerciser 114 may be a conventional integrated circuit tester, such as a model "S15.TM." tester (available from Schlumberger Technologies of San Jose, Calif.) which can repeatedly apply a pattern of test vectors to the specimen circuit over a bus 124. The device (such as an IC which can be in wafer form) 126 is placed in a vacuum chamber 128 of probe 112. Data signifying the locations on device 126 at which the beam is to be directed are sent to probe 112 by data processing system 116 over a bus 122. Data processing system 116 may also be used to control circuit exerciser 114. System 110 can be controlled by an operator who inputs commands through display terminal 118.
Referring to FIG. 2, one such prior-art test probe 112 includes three elements mounted to a surface 225: a stage 226, a probe card 228, and a focused-beam column 229. Column 229 generates a charged-particle beam directed along axis 236. The electron beam passes through openings in surface 225 and probe card 228. The point at which the beam strikes device 126 (shown as a wafer in FIG. 2) is determined by the position of column 229 (controllable by means of an x-y stage 240) and by the deflection of the beam (controllable by means of x-y deflection coils 241 ).
Such systems combine on a single workstation the display of a schematic circuit diagram, layout mask data and a live scanning-electron microscope (SEM) or scanning-ion microscope (SIM) image of the chip, along with analog and/or digital waveforms. The SEM (or SIM), layout and schematic displays in the prior-an Schlumberger systems are linked together to facilitate navigation around the IC chip. For example, when the user pans (moves laterally) or zooms (changes magnification) one of the linked displays, the others pan or zoom accordingly. When the user places a probe icon at a point on one of the linked displays, expected waveforms and actual measured waveforms at that point may be displayed for comparison.
FIG. 3 illustrates an example of linked schematic, layout, and SEM images produced with an IDS 5000 system with the magnification set to produce a relatively wide field of view. The conventional Schlumberger systems display such images in multiple colors to provide the user with additional information such as the layer or net to which a particular displayed feature belongs. Schematic image 310 represents a portion of a circuit embodied in a device. Layout image 320 represents approximately the same portion of the circuit as is displayed in schematic image 310. SEM image 330 represents approximately the same portion of the circuit as is displayed in layout image 320. Examination of layout image 320 and SEM image 330 indicates a close correlation between the displayed circuit features. Superposed on layout image 320 and SEM image 330, respectively, are boxes representing a layout window 340 and a SEM window 350 which delimit the field of view of the probe for a given stage position at an increased level of magnification. As the field of view is zoomed in and out in response to commands from the user, the displayed images zoom in and out correspondingly. Layout window 340 and SEM window 350 represent approximately the same field of view of the circuit once the images have been linked.
When using an EBP system, the operator spends a lot of time searching for the best place to position the electron-beam probe to get the best signal measurement. The best signal is obtained from a probe location that has the highest signal-to-noise (S/N) ratio and lowest cross-talk from neighboring signals. Higher S/N reduces the noise given a fixed waveform acquisition time and lower crosstalk reduces undesirable signal distortions so as to yield a truer waveform.
When using a FIB system, the operator spends a lot of time searching for the best place to cut a probe hole. This hole is cut through passivation on passivated devices to reach the topmost conducting layer, or through inter-layer dielectric on passivated devices and on unpassivated or depassivated devices to reach lower conducting layers. A probe hole can be filled with conducting material or left unfilled. This imposes constraints on the size and position of the hole. The probe hole may or may not be allowed to cut through particular higher-layer conductors to reach signals of lower-layer conductors. For example, cutting through a narrow clock-signal conductor is undesirable, while cutting through a wide power bus may be acceptable. This imposes further constraints on where a hole can be cut. The goal of cutting a probe-point hole is to allow a prober, EBP or mechanical prober (MP), to measure a waveform from a buried signal conductor.
Systems for analytical mechanical probing of sub-micron structures are known which use a manipulator to position a probe needle while the operation is observed with a high-magnification microscope. Such systems are commercially available from sources including Karl Suss, Alessi, and Wentworth. Another type of MP is the atomic force microscope (AFM), in which a sharp probe tip is scanned over a sample surface. Such systems are commercially available from Veeco Instruments, Inc. See, e.g., D. RUGAR et al., Atomic Force Microscopy, PHYSICS TODAY, October 1990, pp. 23-30.
When a computer-aided design/computer-aided engineering (CAD/CAE) system for IC design is used to lay out the mask for a new device, there is little or no consideration of the accessibility of each signal to a probe system. Unlike the area of design-for-testability (DFT), where extra signals and specific structures are added to improve internal signal controllability and observability via the device pins, there is no such design-for-probe modifications provided with most IC design software today. This can result in devices being manufactured which can be tested to find out which pass and which fail, but which cannot be diagnosed using probe methods to find out why and where the failing devices failed.
One prior effort to address this problem is disclosed in U.S. Pat. No. 5,392,222 of Alan C. Noble granted Feb. 21, 1995, the disclosure of which is incorporated herein by this reference. The approach is employed in Optimal Probe Placement (OPP) software from Schlumberger Technologies, ATE Division, Diagnostic Systems Group, as part of the Integrated Diagnostic System (IDS) product family. Unlike the "interactive" methods of the present invention, the OPP methods perform a "batch" mode operation and are based on a different methodology.
In the OPP methods, polygons describing physical structure of the IC device are associated with signal nets of the device. The layout files are processed to successively eliminate those polygons which are deemed unusable for probing. The polygons remaining after such pruning are deemed optimal for probing, and the operator can use any of these. The Dracula Design Rule Checker (DRC) and Layout-Versus-Schematic (LVS) software tools are used to eliminate unusable polygons from consideration. The OPP methods employ polygon resizing rules to shrink or expand polygons by a specified amount, as well as rules for checking overlap of polygons using logical operations such as AND/OR/NOT.
The OPP methods impose a "Width" rule, a "Depth" rule, and a "Proximity" rule on the polygons to determine which are suitable for probing. (Other rules provided with the present invention are not support in the OPP methods.) The Width rules shrinks all polygons by a MinWidth parameter to eliminate all polygons smaller than MinWidth. Referring to FIG. 4, a polygon 400 and a polygon 410 are each reduced in size by MinWidth using Dracula's SIZE command. Polygon 400 is extinguished as shown at 420, but a reduced-size polygon 430 remains of polygon 410. Polygon 430 is then enlarged by MinWidth to provide a polygon 440 equal to polygon 410. The Depth rule finds intersections between polygons of different layers, and eliminates obscured lower layer polygons from consideration using Dracula's AND, OR and NOT operators. FIG. 5 shows a polygon A (500) overlying a polygon B (510) such that a part of polygon B is inaccessible for probing. Application of the OPP Depth rule leaves polygon A (500) and transforms polygon B into polygons C (520 and 530) which are suitable for probing. The Proximity rule oversizes all polygons by a MinSpace parameter, then checks for overlap between adjacent polygons, and eliminates any that overlap. This ensures that polygons closer than MinSpace from a neighbor will not be probed. Dracula's SIZE and CUT rules are used. As shown in FIG. 6, adjacent polygons A (600), B (610), C (620) are enlarged by MinSpace to produce polygons A' (630), B' (640), C' (650). Polygon B' overlaps polygon A', so both are eliminated to leave polygon C" (660). Polygon C" is reduced by MinSpace so that a polygon C'" (670) remains for probing.
Techniques are known for applying a set of probing point selection rules to the complete area of a desired wire with the intent to minimize local field effect, crosstalk and circuit structure influences. See, e.g., R. SCHARF et al., DRC-Based Selection of Optimal Probing Points for Chip-Internal Measurements, PROC. INT. TEST CONF. 1992, Paper 39.2, pp. 840-847. The Scharf et al. method requires topological computations like Boolean operations or sizing, which are provided in commercially-available design rule check (DRC) tools. See also P. GARINO et al., Automatic Selection of Optimal Probing Points for E-Beam Measurements, EOBT, 1991, Como, Italy, pp. 88-96; R. SCHARF et al., Layout Analysis and Automatic Test Point Selection for Fast Prototype Debug using E-Beam or Laser-Beam Testsystems, IEEE Custom Integrated Circuits Conference (CICC), 1992, Boston, Mass., U.S.A., pages 17.3.1-4; R. SCHARF et al., CAPT/IVE: Computer Aided Prototype Testing using an Integrated Verification Environment, Northcon/91, 1991, Portland, Oreg., U.S.A., pp. 370-375; K. HERRMANN et al., Design for e-beam testability--A demand for e-beam testing of future device generations?, MICROELECTRONIC ENGINEERING, Vol. 7, 1987, pp. 405-415; W. LEE, Engineering a Device for Electron-Beam Probing, IEEE DESIGN & TEST OF COMPUTERS, Vol. 6, 1989, pp. 36-49; A. NOBLE et al., Increasing Automation in Diagnostic Processes, EE-EVALUATION ENGINEERING, Vol. 5, 1992, pp. 10-14.
While methods employing a variety of EBP placement rules are known from the above, none is believed comprehensive enough to direct probe-point cutting operations where a FIB or laser-beam is to be used in combination with an EPB or MP, and none is believed suitable for interactive (rather than batch) operation.